The present invention relates to a general purpose digital data processing system. More particularly, it relates to an improved cache memory means for such a digital data processing system.
One of the aims of improved computer systems is the enhancement of the data throughput of the system. In fulfillment of this aim, a computer system has been provided in which the central processor unit includes a plurality of execution units which may be actuated for concurrent operation. Such a central processor unit is shown and claimed in the co-pending application of William A. Shelly and Leonard Trubisky, Ser. No. 434,122 filed 10/13/82 which issued as U.S. Pat. No. 4,521,851 on June 4, 1985. It is well known to provide high speed cache memory units for the temporary storage of data for the use of the execution units. To further enhance the throughput of such computer systems, it has been proposed, as in U.S. Pat. No. 3,618,041, to provide a dual cache means wherein the cache memory appears as two separate cache elements or units, one exclusively for instruction data and the other exclusively for operand data. Such a dual cache approach, while providing a measure of improvement, still falls short in optimizing the throughput time of the computer system. The dual cache arrangement of previously disclosed systems do not provide a high degree of versatility in the handling of data for the system.